Overview
As a Field-Programmable Gate Arrays (FPGA) Engineer, you will play a key role in designing, implementing, and verifying innovative FPGA solutions tailored for advanced microwave and control applications. Collaborating closely with Embedded Software, Firmware, and Hardware Engineers, you will contribute to the development of high-performance computing systems, ensuring the robustness, scalability, and maintainability of FPGA architectures.
Responsibilities
- Design and verify complex FPGA logic using SystemVerilog for high-performance hardware applications.
- Build scalable RTL, high-speed interfaces, and DSP pipelines for ADCs, DACs, memory devices, and RF SoC platforms.
- Fine-tune FPGA designs for deterministic timing, timing closure, multi-clock domain synchronisation, and optimal resource utilisation.
- Perform rigorous FPGA verification, laboratory debugging, integration, and system-level validation against technical requirements.
- Establish communication, synchronisation, and data transfer interfaces across distributed hardware systems.
- Work seamlessly with internal engineering teams, supporting supplier and external development activities as needed.
- Produce comprehensive FPGA architecture, interface, and implementation documentation to ensure traceability and long-term maintainability.
Requirements
- Proven commercial experience delivering complex FPGA design, verification, and integration projects.
- Strong development expertise using SystemVerilog for advanced FPGA applications.
- Hands-on experience developing high-speed ADC, DAC, and memory interfaces.
- Deep expertise in deterministic timing, multi-clock domain design, and synchronisation.
- Solid understanding of FPGA architecture, RTL development, and rigorous verification methodologies.
- Strong background in timing analysis, constraint definition, and achieving timing closure.
- Experience implementing DSP algorithms on FPGA platforms and modelling experience with MATLAB or Simulink.
- Practical experience working with RF SoC platforms and high-speed digital data transfer architectures.